Buried floating gate structures in EEPROM devices are known as an alternative to customary floating gate devices where the floating gate is an isolated poly layer separated from the substrate by tunnel oxide. For example, U.S. Pat. No. 6,052,311 to Fu shows a floating gate within a substrate. Source and drain electrodes are located beside the floating gate and the control gate is located over the surface of the substrate above the floating gate and insulated from the floating gate. The patent teaches that a way to reduce the time for programming and the erasing the device is to enlarge the overlap between the floating gate and the control gate, that is, to raise the capacitive coupling ratio of the device. Another way to shorten programming and erase time is to increase voltage used for these operations. Because of shrinking device sizes, increasing voltage and concomitant power consumption is not a preferred alternative. Partially buried floating gate structures are shown in U.S. Pat. No. 6,720,611 to Jang and U.S. Pat. No. 6,906,379 to Chen et al.
One of the interesting aspects of the device of the '311 patent is that the channel region is shifted in a position to a location between the source and drain electrodes, but below the subsurface floating gate. In other words, the floating gate occupies the space normally occupied by the channel.
An object of the invention is an EEPROM device which is programmable with low voltages but that has fast programming and erase times.